The present invention relates to techniques for providing multiple on-chip termination impedance values to pins on an integrated circuit, and more particularly, to techniques for providing different termination impedance values to different pins on an integrated circuit using by shifting digital bit signals.
Prior art integrated circuits have off-chip termination resistors. An off-chip termination resistor is coupled to each input/output (I/O) pin of an integrated circuit to provide termination impedance. The impedance of each off-chip resistor matches the impedance of a transmission line coupled to the pin to reduce signal reflection.
Some integrated circuit have hundreds of I/O pins that require impedance matching circuitry. In these integrated circuits, a separate impedance matching resistor must be coupled to each of the I/O pins. Hundreds of impedance matching resistors must be coupled to such an integrated circuit to provide adequate impedance matching. Thus, prior art off-chip impedance matching resistors substantially increase the amount of board space required.
Other prior art integrated circuits have provided on-chip impedance termination techniques. However, these on-chip impedance termination techniques provide the same impedance termination values to one or more I/O pins on the integrated circuit.
Different I/O pins on an integrated circuit are typically coupled to different transmission lines that have different characteristic impedance values. Providing the same impedance termination values at each pin does not produce the right impedance matching values that are needed to reduce signal reflection on all of the transmission lines. Therefore, it would be desirable to have circuitry that can match the characteristic impedance of transmission lines with different characteristic impedance values without requiring numerous off-chip resistors.